Field of the Invention
The invention relates to methods and apparatus for calculating substrate model parameters, to methods and apparatus for controlling lithographic processing and to computer program products for implementing such methods and apparatus. The substrate model parameters can be used for example in models for correcting errors of overlay and alignment in lithographic processing.
Related Art
A lithographic process is one in which a lithographic apparatus applies a desired pattern onto a substrate, usually onto a target portion of the substrate, after which various processing chemical and/or physical processing steps work through the pattern to create functional features of a complex product. The accurate placement of patterns on the substrate is a chief challenge for reducing the size of circuit components and other products that may be produced by lithography. In particular, the challenge of measuring accurately the features on a substrate which have already been laid down is a critical step in being able to position successive layers of features in superposition accurately enough to produce working devices with a high yield. So-called overlay should, in general, be achieved within a few tens of nanometers in today's sub-micron semiconductor devices, down to a few nanometers in the most critical layers.
Consequently, modern lithography apparatuses involve extensive measurement or ‘mapping’ operations prior to the step of actually exposing or otherwise patterning the substrate at a target location. In the following discussion, the substrate will be referred to for convenience as a “wafer”, without implying any limitation to the types of substrate that may be processed using the invention. Advanced substrate models, for example alignment models, have been, and continue to be, developed to model and correct more accurately non-linear distortions of the wafer grid that are caused by processing steps and/or by the lithographic apparatus itself. The expression wafer grid is used to refer to a coordinate system that is formed by the (measured) alignment marks at the wafer. For example, a wafer grid is formed by the alignment marks in the scribe lanes of the wafer, that in the ideal case form an orthogonal grid.
Alignment model parameters are calculated in order to fit an alignment model to measurements of structures on substrates. Overlay and alignment error on production wafers as function of a position on the wafer can described by means of alignment models. These alignment models are used in automatic process control (APC) systems to control lithographic processes to correct for overlay and alignment errors. However, it has been found that even with such correction, there is still yield loss at the edge of the wafer. To correct this yield loss using known modelling techniques would introduce a high burden on measurement and on computation.